Propagation Delay

Any physicist will tell you that an event at one location in space cannot instantly cause an effect somewhere else in space. This fundamental speed limit of the universe means that if we have a logic circuit and one of the inputs changes value, we should expect some delay before the output changes. In fact, in electronic circuits, the delay is far more than the fundamental speed limit of the universe, because electrons need to move around for voltages to change. And it's worse yet in CMOS logic, because the gates of FETs have a significant amount of capacitance, which means that more electrons need to move for the voltage to change.

The delay between an input changing and an output changing (whether it's a single gate or a larger circuit) is called propagation delay -- literally the time it takes for the change to propagate through the circuit.

Propagation delay can be estimated before manufacturing a digital device (again, whether that's a single gate or a more complicated circuit), so, while testing the final physical device is important, performing analysis during the design process is important as well. When using existing parts or processes, manufacturers will characterize their devices by testing propagation delay (among other things), and they will summarize the specifications for a particular type of device in a datasheet.

That means that usually we, as engineers creating digital systems, can look up the characteristics of the devices that we intend to use. If we are using a NAND gate in our circuit, the manufacturer of whatever NAND gate we intend to use will have already determined the expected propagation delay, and we can use that information to predict the behavior of our circuit.

Simulating Timing Behavior

Consider the following circuit. The gates have been labeled with their expected propagation delays (as would be specified by the manufacturer) -- in other words, the expected amount of time between an input changing and the output changing in response to that event.

We can now simulate the response of the circuit to changing inputs. A common way to visualize this is with a timing diagram (or timing simulation), which plots the logic state (high or low) of signals in the circuit over time. Below is a timing diagram of the circuit, currently with a blank output because we have not yet simulated it, but with the input waveforms defined. All of the inputs start low, then A goes high at t=5ns, etc.

Since the output depends on an intermediate signal, the output's timing behavior cannot be determined without knowing what that intermediate signal does, so it has also been added to the diagram, labeled with its expression.

The currently-unknown signals (everything except the inputs) have been given initial values based on the initial values of the inputs.

To determine what the B+C signal does, any change on the inputs of the OR gate should be evaluated, but changes to the output of that OR gate will be delayed by 5 ns. For example, at t=15 ns, B goes high, which will cause B+C to go high, but that change will happen at t=20 ns. Likewise, the signal goes low at 30  because the OR gate's inputs were both low at 25 ns.

Now that B+C is known, the AND gate's inputs are all known. It is critical to realize that the inputs B and C do not directly affect the AND gate. The only things that matters to the AND gate are its inputs, and its inputs are the signals A and B+C.

• At t=5 ns, input A goes high. However, B+C is still low, so that change does not cause a change on the output.
• At t=20 ns, signal B+C goes high. At this point, both of the AND gate's inputs are high, so its output will go high, but that change will happen 7 ns later.
• You cannot simply skip ahead to 27 ns! Another relevant event happens at 25 , when A goes low. This will cause the output to go low, but of course that happens 7 ns later.
• B+C goes low at 30 ns, but since the output is already low, that has no effect.

The arrows here are to highlight the events that cause the changes in the output.

Timing Hazards

As changes propagate through the gates of a circuit, it is possible for brief glitches to occur on the output. Consider this circuit. Intermediate nodes have been labeled (D and E) to make labeling the timing diagram easier.

From a functional standpoint (i.e., only considering the logical behavior of the circuit and not timing effects), if the inputs ABC are 000 or 010 (A and C low, B either low or high), the output should be high. However, observe what happens when B changes. In this timing diagram, all gates are assumed to have 5 ns propagation delay, and the A and C signals have not been included because they would just be constant 1.

When B goes from 0 to 1, nothing interesting happens, but when B goes from 1 to 0, a pulse occurs on the output. The reason this happens is that, even though functionally (i.e. not considering timing) the bottom AND gate's output is going low and the top AND gate's output is going high, the change in the top AND gate is delayed by the inverter, so there is a period of time when neither AND gate is outputting high.

These situations are called timing hazards, and the unintended pulses are called glitches. Engineers sometimes distinguish between two types of timing hazards:

• If a signal is expected to remain constant but it experiences a glitch, it is called a static hazard.
• If a signal is expected to change but it changes multiple times in the process, it is called a dynamic hazard.

Both types cause unexpected and possibly undesirable values on the output, and in some situations they need to be addressed, but that is beyond the scope of this course. What is important here is understanding how changes propagate through a logic circuit and being able to simulate those changes in specific situations.

Summary

• After the input of a gate changes value, it takes some time for the output to change. This time is called propagation delay.
• By assuming certain propagation delays, the timing behavior of a circuit can be simulated.
• The response of a circuit to a specific sequence of input values can be plotted in a timing diagram.