Gate Schematic Symbols

Visual representations of systems are common throughout engineering. Building plans, system diagrams, process flow charts – they could all be described using words and formulas, but often a picture is easier and more effective.

In electrical engineering, we have circuit schematics. You have seen several examples already -- in the previous topic (CMOS), we used schematics to show how FETs can be connected to create circuits that can control the voltage on an output node based on the voltages on some input nodes, thus implementing some digital logic.

The reason to use voltage for the output signal was because the inputs are controlled by voltage, which means that the output of one CMOS system can be used to control another system. In a schematic, that would be depicted with a wire from an output of one CMOS structure connecting to an input of another CMOS structure (i.e. the gates of FETs). Although arbitrarily-complex combinational logic can be implemented by chaining together these small pieces, the schematic quickly becomes difficult to create and to interpret.

Instead of drawing all of the transistors and all of their connections as we did when creating switch-level schematic representations of CMOS circuits, engineers often prefer to abstract away those lowest levels of logic implementation and use schematic symbols to directly represent logic functions. The simplest physical logic devices -- ones that implement basic logic functions -- are called logic gates. The fundamental Boolean operations (discussed in the section on Boolean logic) each get a schematic symbol to represent a gate that implements that function. Gate-level schematics traditionally flow from left to right, so in the following symbols, the inputs to the gates are on the left, and the output of each gate is on the right.

In the previous topic on CMOS, we designed a logic gate (at the switch level) for the function A·B, and we found that it worked very conveniently with respect to using P-FETs and N-FETs appropriately in the pull-up and pull-down networks. If you try that with A·B, it does not work out so nicely, and, likewise, A+B works out much better than A+B. Because of this, it makes sense to have a gate symbol for those logic functions, and in fact they get their own names as well.

In the symbol for the NOT gate (also called an inverter), it is the bubble on the output that represents the logical inversion. This bubble can be added to the other gate bodies to create symbols for NAND ("NOT AND," A·B) and NOR (A+B) gates:

A benefit of gate-level design is that the specifics of the implementation are hidden. Although we covered CMOS, there are other ways to implement logic gates (TTL is a common one), and there are phases of the design process where implementation is not important. Designing logic circuits with gate symbols still explicitly shows how components will be connected to one another (unlike an expression), but it does not specify things like using FETs to physically create the gates.

Gate Schematics

Since both the output and inputs of each gate is a voltage, complicated logic systems can be created by connecting simple components.

A diagram of how gates connect to each other is a gate schematic. Here is a gate schematic that implements A∙B+B∙C+A∙C:

Here are some things to pay attention to in this schematic and gate schematics in general:

• The input and output signals are labeled with their names. It is not relevant to this schematic where those inputs come from and where the output goes -- this schematic just describes this piece of logic.
• When wires intersect, it is common to put a dot on the intersection to emphasize that they are connected.
• When wires cross but do not connect, it is common to put a jump to emphasize that they are not connected.
• However, some schematics will not use dots or jumps, in which case it is necessary to infer from the rest of the schematic whether crossing lines means the wires are connected or not.
• Signals can branch out to multiple destinations, as seen in this example with the input signals. This is called "fanout".
• Order of operations is inherent in the connections. The 'B' signal is inverted, and the result of that is ANDed with C, and the result of that is ORed with the other terms of the expression.
• A NAND and NOR were used here, but it would be logically equivalent to use an AND and OR followed by inverters. Which type of gate you use depends on the situation and on the purpose of the schematic.
• Gates can have more than two inputs. The AND and OR logic operations are commutative and associative, so if there are multiple terms ANDed or ORed together, that operation can be performed by a single gate.

Deriving a Boolean expression from a gate schematic requires ensuring that the expression's order of operations matches the schematic. Consider this schematic:

The B+C result fans out and is used in two places. There is no way to represent this in a Boolean expression other than repeating the term. And since the ANDs with A and with C would take precedence over the OR, the B+C must be enclosed in parentheses. The AND terms do not need parentheses, because the final OR will come last when evaluating the expression, just like it does in the schematic.

F = A∙(B+C)+D∙(B+C)

(Quick reminder: 'F' is not "equal" to that, it is defined by that. The logic produces F from A, B, C, and D.)

Mixed Logic

It is worth remembering at this point that logic high and logic low voltage are being used in these systems to represent whatever information we (as the engineers) want to represent. It is also important to note that nothing requires logic high to be used to represent "true" and logic low to represent "false" -- that convention, called "positive logic," just works best with our brains, so it tends to be the standard.

However, imagine you are designing some logic to indicate that a printer is ready as long as it has paper in at least one of its two trays. The printer's trays are fitted with sensors that output logic high voltage when the tray is empty and logic low voltage when there is paper. We might decide that we want to think of these signals in the positive sense ("there is paper"), but if we design this system considering low voltage to be "true," then we are going to get confused when we need to integrate this circuit with others that have been designed with low voltage representing "false".

Instead, it would be nice if we could decouple what we mean from how we implement it. This is where mixed logic comes in.

In mixed logic, we separate the activation level (whether high or low voltage represents "true") from the logic operations. A mixed logic schematic for the above situation would look like this:

• The OR gate body expresses that either input being active makes the output active.
• The bubbles on the inputs indicate that those signals are "active-low"; i.e. logic low voltage is used to represent their "active" state.
• The lack of a bubble on the output indicates that the output is active-high.

The gate symbol used there is called a "bubbled OR" gate, or BOR. However, if you implement a BOR gate (for example, with CMOS), you end up with exactly the same thing as you do if you implement a NAND gate, because those two logic functions are the same (by DeMorgan's theorem). The only reason to draw the schematic symbol as a BOR rather than a NAND is to express meaning. They are logically identical, but semantically different.

By applying DeMorgan's theorem, there are four pairs of logically-equivalent basic gates:

AND, OR, NAND, and NOR are considered the "standard" forms, but BAND, BOR, BNAND, and BNOR exist for situations where you (the engineer) want to express a specific meaning or intention.

Mixed Logic Manipulation

Since mixed logic helps separate purpose and implementation, another use for it is to help create a desireable implementation based on a given purpose. Consider the previous situation, where an output needs to be produced from the OR of two active-low inputs. Instead of immediately creating a final gate schematic, an intermediate step can be created:

Instead of drawing inverters, bars have been placed on the wires where an inversion needs to occur. In this situation, the inversions are required because the inputs are active-low, but we intend to create a circuit that will use active-high physical components, because that is the common convention.

This schematic is not particularly useful though because it currently lacks an implementation. The bars on the wires do not represent implementation, they represent intention. To actually create a circuit from this schematic, we must complete the implementation, and we can use mixed logic to gain flexibility in that implementation. To create an implementation, we need to resolve the necessary inversions (represented by the bars). We could do that by simply adding inverters:

In this schematic, inverters have been added to implement the inversions indicated by the bars, and the bars have been marked with bubbles to indicate that they are handled. It bears repeating that the bars, and the bubbles placed on bars to mark them as handled, do not represent implementation, and if this circuit was built, the bars and bubbles would not become anything physical! The added inverters, on the other hand, would be physical devices, because they were added as part of the implementation.

The above implementation is not the only one possible though. Consider this implementation:

Note that even though BOR is logically equivalent to NAND, we do not replace the schematic symbol with a NAND symbol. The fundamental purpose of mixed logic is to separate intention from implementation, and the intention of this logic is OR (if tray 1 has paper OR tray 2 has paper). Drawing a NAND gate would destroy that meaning.

However, it is worth mentioning that you cannot purchase a BOR or BAND or the other bubbled-input gates. Because they are literally equivalent to other forms (AND, NOR, etc.), manufacturers call their products by those names; it would be pointless for them to sell both NAND gates and BOR gates. So if you were building a circuit with a BNAND in it, you would purchase an OR gate.

Since there is flexibility when deciding on an implementation for a mixed logic schematic, we can take advantage of that flexibility to create an implementation with specific goals in mind. The two main goals are usually to either

• minimize the number of transistors (the implementation cost), or
• use a specific type of gate (often to use only one type of gate to consolidate required hardware).

Consider this starting point, and assume that the desired implementation is to only use NAND gates and inverters:

To create the implementation, the first step is to get all of the gate bodies into the correct form. That means that a bubble needs to be added to the outputs of any AND bodies, and bubbles need to be added to the inputs of any OR bodies to make them BORs, which is the equivalent of NAND. However, to preserve the logic, bubbles must always be added in pairs (since, by the double complement rule, that logically cancels out and creates no logical change).

This will be the result of the right side of the schematic after implementation, with the additions highlighted in red:

In some places, adding bubble pairs works entirely to our advantage. For example, at the top, a bubble pair can be added to the output of the AND and the input of the OR, which gets us closer to the desired implementation, in a sense, for free. And at the bottom, a bubble can be added to the input of the OR body and its pair used to handle the necessary inversion indicated by the bar -- essentially saying "this signal no longer needs to be inverted, because the gate is performing OR on active-low inputs."

But sometimes a bubble is needed in one place, but the other bubble can't be used for anything. In that case, like with the middle wire above, an inverter must be added to be the other bubble. Remember, this will be a real, physical inverter in the implementation.

When there is fanout, if a bubble pair gets split up across the branch, all branches must have bubbles. This requires some consideration to decide if it is better to cancel a bubble before the branch or to push it through. In this part of the circuit, it is optimal to use a single inverter and use the two other bubbles to cancel a bar and to help turn an OR body into a BOR.

By following the rules for adding bubbles, all gates can be converted to a specific form, and all bars can be accounted for, thus creating a desired implementation. This is the result of converting the above example to all NANDs and inverters:

Note that to help keep track of where bubbles came from, they are placed on the left or right of bars and inverters to keep bubble pairs together. A good example of this is on the output. Pay particular attention to the fact that the triangle still faces forwards; it is just the bubble that moved.

Here is what the implementation would be if using only NORs and inverters:

It turns out that this implementation only requires two inverters, so if given a choice, it would be preferred over the NAND implementation. Though leaving it as an AND or making it a NAND followed by an inverter could be even better in some ways, but the requirement here was to use only one type of gate, so that's what was done.

Summary

• Logic gates have inputs controlled by voltage and they output voltage, so they can be chained together to design more complicated logic circuits.
• Gate schematics are a graphical tool for designing logic.
• Gate schematics provide an opportunity to separate physical logic levels from logic design using a technique called mixed logic.
• Mixed logic can also be used to manipulate schematics to achieve a particular physical implementation.