FETs
When we discussed implementing logic with switch networks, it was not clear how the switches were getting activated. Perhaps it was someone pushing them, or maybe trained parakeets named A and B were flipping them on and off. Neither of those methods will work if we want to create electronic devices with thousands or billions of switches. We need a type of switch that not only controls electricity, but can be controlled by electricity.
Many devices have been invented to fulfill this need, from electromechanical relays to vacuum tubes, but the transistor is what allowed computers to go from room-filling behemoths to pocket-sized wonders. A specific type of transistor called a MOSFET is usually used in modern digital electronics because of its low power requirements; when putting billions of transistors in a small area, if each requires any more than a minuscule amount of power, the device will quickly catch fire.
MOSFETs (often shortened to "FETs") behave like switches: they have two terminals that current can flow between (or be prevented from flowing between), called the source and drain. Since FETs are electrically-controlled, they also have a terminal for a control signal, called the gate. A high or low voltage on the gate controls the connection between the source and drain.
FETs come in two main varieties: N-channel FETs (often shortened to N-FET or NFET) and P-channel FETs (P-FET or PFET). They behave like normally-open and normally-closed switches, respectively (if high voltage on their gate is considered "active").
Note that there are dozens of different types of transistors, each of which can be tweaked in hundreds of different ways and used in thousands of different applications, including in analog electronics. This discussion ignores almost all of that, focusing only on what is needed for a conceptual understanding of basic CMOS.
CMOS Overview
Just like with the generic switches discussed earlier, switch networks can be created with FETs to implement logic functions. With switch networks, the input is whatever controls the switches, so with FETs, the inputs are voltage. The 'output' of a switch network is whether or not there is a connection through the network, but if FETs are controlled by voltage, it would be convenient to create a system where the output is also voltage, because then the output from one system could be directly used as an input for another system. In digital electronics, one way of accomplishing that is called Complementary MOS, or CMOS. The "MOS" refers to the use of MOSFETs, and the "complementary" refers to the fact that each system contains a complementary pair of switch networks: a pull-up network and a pull-down network.
To create an output with a defined voltage, that output must be connected to a source of defined voltage. In an earlier lesson, a battery was used as a source of voltage. The actual source doesn't matter, but we will continue to use the battery symbol here since it is conceptually convenient. The positive end of the battery will be the definition of "high" voltage, and the negative end will be the definition of "low" voltage, so in order to force an output to have high or low voltage, switch networks need to be designed to connect the output to those points.
Note: "High voltage" has a common definition in power electronics, where it refers to systems operating at hundreds or thousands of volts. That definitely does not apply here, so from now on, the terms "logic high" and "logic low" will be used to refer to the high and low voltage in these digital systems.
To avoid needing to always draw wires to the voltage source, we will use source symbols. Every instance of these symbols is connected to the voltage source, so the following circuit is exactly the same as the one above:
In different schematics, the "Vcc" label might be "Vdd" or "V+" or "+V", but it means the same thing: a connection to the source of high voltage. The connection to low voltage might be a triangle like this, or a slightly different ground symbol, or a label of "0V" or "gnd" or "V-".
Pull-up and Pull-down Networks
Creating the pull-up and pull-down networks starts by deciding when those networks should have a path through them. Remember that the pull-up network's purpose is to connect to logic high (which we will consider 'true' and represent with '1'), and since the desired function is already the definition of when the output should be true, the function also describes when the pull-up network should have a path through it.
The pull-down network is responsible for connecting the output to low voltage when the output should be false. The expression for when the output is false is just the inverse of the desired function, so to get an expression for when the pull-down network needs a connection through it, you can simply invert the desired output function.
Consider the function A·B. The function already describes the required pull-up network, and the inverse of the function, A·B, describes the required pull-down network.
As mentioned in a previous section, switch networks can only be created for expressions with inversions over single inputs, so A·B needs to be manipulated with DeMorgan's theorem to A+B.
Now the pull-up and pull-down networks can be designed at the switch level, keeping in mind that P-FETs behave like normally-closed switches and N-FETs behave like normally-open switches, and the networks can be connected between the voltage source and the output node:
Correct behavior can be confirmed by testing each input case:
| A | B | pull-up path? | pull-down path? | result voltage | result logic |
|---|---|---|---|---|---|
| 0 | 0 | yes | no | high | 1 |
| 0 | 1 | yes | no | high | 1 |
| 1 | 0 | yes | no | high | 1 |
| 1 | 1 | no | yes | low | 0 |
Larger Circuits
A CMOS circuit can be created to implement any logic. Let's create CMOS for A+B+C.
The first step is to create expressions for the pull-up and pull-down networks that are appropriate for switch-level implementation. The desired logic already describes the pull-up network, but big bars need to be broken down, giving A·B+C. The expression for the pull-down network can be derived by inverting the pull-up expression, and since that would then necessitate breaking down that big bar using DeMorgan's theorem, the whole process can be accomplished at once by inverting each input and swapping ANDs and ORs, being very careful to add parentheses when needed to maintain order of operations: (A+B)·C.
The pull-up and pull-down networks can then be connected to the voltage source and the output, but this time there's a problem. Because of how FETs work (reasons which are beyond the scope of this course), P-FETs work best when used to implement the pull-up network, and N-FETs work best when used to implement the pull-down network. In the example above, that conveniently happened anyway, but directly implementing the switch network expressions for this new system would require an N-FET in the pull-up network and a P-FET in the pull-down network, which should not be done.
The solution is to use the necessary FETs, and to invert the necessary input(s) using another CMOS structure:
Often when creating CMOS logic, we will just assume that complemented inputs are available, since getting them is simple if it is needed.
Summary
- The electronic switches used in most modern digital logic are called MOSFETs.
- Digital logic can be implemented entirely electronically by using those voltage-controlled switches and creating systems for which the outputs are also voltage.
- To create an output of voltage, two switch networks are used: a pull-up network to connect the output to the source of logic high voltage, and a pull-down network to connect the output to the source of logic low voltage.
- There are two types of FETs (relevant to this topic): N-FETs, which behave like normally-open switches, and P-FETs, which behave like normally-closed switches.
- Because of physical limitations, P-FETs should be used in the pull-up network of a CMOS device, and N-FETs should be used in the pull-down network.
- Designing the switch networks often requires manipulating the expression for the desired logic function: to break down all big bars, and to invert the logic to get the expression for the pull-down network.